An Introduction to Digital Logic Familities

• With either input at 0V,
  V_x=0.7 V, D_L is just cut off,
  and V_OUT = 0 V.
   
• With both inputs at 1 V,
  V_X=1.7 V and V_OUT=1 V.

• If all inputs are high, V_x = 2.2 V and
  the transistor is saturated.

• If any input goes low (0.2 V), V_x = 0.9 V
  and the transistor cuts off.
   
• The added resistor R₂ provides a discharge
  path for stored base charge in the BJT, to
  provide a reasonable L->H transition time.

ï Q₁ is reverse active.
ï Q_O is saturated.
ï V_OL = V_CE(sat)

ï Q₁ is saturated.
ï Q_O is cut off.
ï V_OH = V_CC

Low to High Transistion
• The time required to discharge the Q₁ depletion layers is << 1ns.
   
• The time required to extract the Q₂ base charge is also << 1ns:
  • Q₁ becomes forward active;
  • IBR becomes large for Q₂
• Removal of base charge from Q_O is similar to the DTL case.  With R₂ = 1 kW, t_s = 10ns (typical values for 7400 series TTL).

High to Low Transistion
• The depletion capacitance of the Q₁ EB junction must discharge;
   
• Base charge must be removed from the saturated Q₂
   
• Ditto for Q_O
   
• The capactive load must be charged to V_CC.

Click on image to enlarge

• The Schottky diodes can be made smaller than Q₁, with lower parasitic capacitances, with post 1975 technology (6mm features).
   
• Q_S can not saturate, so it is not neccessary to remove its base charge with a BJT.
   

  
   
   
   
   
   
   

  (source)