| Week | Date | Content | Exercise |
|---|---|---|---|
| 1 | 2/19 | An overview of the course | |
| 2 | 2/26 | Ch 1 | Exercise 1 (Ch 1, due: 3/12 14:00) |
| 3 | 3/5 | Ch 1, Ch 2 | |
| 4 | 3/12 | Ch 2 | Exercise 2 (Ch 2, due: 3/26 14:00) |
| 5 | 3/19 | Ch 2 | |
| 6 | 3/26 | Ch 3 | |
| 7 | 4/2 | Ch 3 | Exercise 3 (Ch 3, due: 4/16 14:00) |
| 8 | 4/9 | 1. Ch 3 2. A review of Ch 1 to Ch 3 | MIPS programming (due: 4/29 23:59:59) |
| 9 | 4/16 | Midterm exam | |
| 10 | 4/23 | 1. A review of the midterm exam 2. Ch 4 (single cycle CPU) | |
| 11 | 4/30 | Ch 4 (pipeline) | Exercise 4 (Ch 4: single cycle CPU, due: 5/14 14:00) |
| 12 | 5/7 | Ch 4 (pipeline hazards) | |
| 13 | 5/14 | 1. Ch 4(instruction-level parallelism) 2. Ch 5 (memory hierarchy) | Exercise 5 (Ch 4-2, due: 5/28 14:00) |
| 14 | 5/21 | 1. Ch 5 (cache) | |
| 15 | 5/28 | Ch 5 (virtual memory) | |
| 16 | 6/4 | 1. Ch 5 (virtual memory) 2. A review of Ch 4 to Ch 5 | Exercise 6 (Ch 5, due: 6/18 14:00) |
| 17 | 6/11 | GPU, TPU, and systolic array | |
| 18 | 6/18 | Final exam |